1. Field of the Invention
The present invention relates to a circuit and a method for detecting digital data and used in a communication device, etc. having a phase control loop circuit (which is called a PLL circuit in the following description) for inputting data outputted from another electric device and synchronizing an internal clock signal with these input data.
2. Description of the Related Art
A data-receiving clock reproducing circuit is generally constructed by a circuit for detecting a data-changing point, a counter and a reset control circuit. A known phase control loop (PLL) circuit detects changing points in all data.
Such a phase control loop circuit has preferable follow-up characteristics with respect to the frequency of a transmitted clock signal. However, no countermeasure with respect to noises is taken in this phase control loop circuit. Accordingly, an operation of the phase control loop circuit is adversely affected by the noises.
Therefore, Japanese Patent Application Laying Open (KOKAI) No. 60-245351 discloses a method for detecting digital data and removing the influence of noises to accurately detect a data-changing point at any time. In this detecting method, a time series of detecting clock signals is formed in synchronization with an internal clock signal between respective bits of the digital data. Voltage levels of the digital data are respectively detected at timings of these detecting clock signals. The influence of a spike noise is removed by a majority operation of the plural detecting data provided by detecting these voltage levels so as to detect a position of the data-changing point. A timing for forming a receiving clock signal synchronized with the internal clock signal is controlled on the basis of this detection of the position of the changing point. Thus, a shift in synchronization of the detected digital data is prevented.
In many cases, the spike noise is caused with respect to data inputted to a communication device on a line for transmitting these data from a transmitting side of these data to a receiving side thereof. Further, in many cases, a jitter is caused at the data-changing point so that a period of the data-changing point is irregularly changed.
Accordingly, it is necessary to operate a phase control loop by the internal clock signal and the input data in a receiver so as to detect data on the signal-transmitting side without any error.
In the above general digital data detecting method, it is possible to remove the influence of a spike noise. However, a reset circuit of the phase control loop is operated at a changing point of the jitter so that a shift in synchronization of the digital data is temporarily caused, thereby causing an error in detection of the data.
Further, in the above detecting method, a timing for performing a resetting operation of the reset circuit is delayed as the number of samplings is increased to improve sensitivity with respect to noises, thereby reducing frequency follow-up characteristics. In contrast to this, when the number of samplings is reduced, the frequency follow-up characteristics are improved, but the sensitivity with respect to noises is reduced. Further, noise states on a line are different from each other in accordance with the communication device or a line distance. Namely, the number of noises is reduced on a certain line, but are increased on another line.
Accordingly, in accordance with the above general detecting method, the communication device can be used on a line providing a small noise, but cannot be used on a line providing a large noise. Further, the communication device can be used on the line providing a large noise, but has a reduced communication quality on the line providing a small noise.